Data processing systems consist of electronic components that are customarily fabricated in integrated circuits upon silicon chips. These integrated circuits include the transistor, resistor and capacitor elements required to perform the circuit functions. The layout or arrangement of these circuit elements upon the silicon chip is critical in achieving high density circuitry arrangements on integrated circuits. Input/output circuits provide a special challenge in the layout of integrated circuits since it is the input/output circuits that provide the interface between the "outside world" and the internal integrated circuit chip functions.
One typical prior art approach to fabricating input/output circuits is termed the reserve cell approach. Examples of the "reserve cell approach" are illustrated in U.S. Pat. Nos. 4,731,643 and 4,746,966. According to the reserve cell technique, specific areas are set aside on the integrated circuit chip for the input/output circuits. Typically, these areas or cells are on the perimeter of the circuit chip since the input/output circuit connections to external circuits are traditionally on the edge of the integrated circuit chip. These areas are sufficient for the input/output circuit for the maximum anticipated function, including the drive, receive, pull-up and other circuit functions (each for the maximum device size). This number of reserved areas or reserved cells fixes the maximum number of input/output circuits permitted for the semiconductor chip design. Typically, a set of compatible circuit layouts are provided that implement each of the basic input/output functions required, such as the drive function, the receive function, etc. The designer would then select among these primitive layouts to construct the total function desired. These components would then be placed in their preplanned locations within the given input/output cell. Productivity with this method is usually excellent because each primitive function only needs to be laid out once. However, the resulting density of the integrated circuit design is poor for several reasons. First, input/output cells must be spaced apart from each other in anticipation of the worst possible neighboring circuit layouts. Second, specific space must be reserved in the cells for the largest anticipated specimen of each type of primitive input/output function. Third, any unused input/output cell space cannot be turned over to internal functional circuits because it is fragmented and, therefore, difficult to place or wire efficiently. Fourth, input/output circuit layouts are commonly coupled to the package connection pitch (or output pin pad connections). These input/output connection constraints often set the limit to input/output circuit density.
A second type of traditional approach to input/output circuit design for integrated circuits is termed the "integrated function" approach. The integrated function approach is actually a full custom design method. In other words, no specific area is set aside for the input/output circuits. Traditionally, the input/output circuits always appear upon the perimeter of the integrated circuit chip. Again, this is because the input/output circuits provide the interface to the "outside world" which means that the input/output circuits are connected directly to the external pad connections upon the perimeter of the chip. According to this method, a complete layout is done for each combination of input/output primitive functions. If, for example, one function had two driver types, two receiver types and a pull-up load resistance, as many as three times three times two or 18 layouts might be required. The number of layouts is further multiplied if various form factors are desired. For example, a form factor can be any one of the following: (1) a tall thin layout, (2) a square layout, (3) an "L" shaped layout or (d) two layouts: one for each orientation with respect to the wiring grid. The end result can be that every input/output circuit becomes a custom layout. This approach results in an integrated circuit design that can be very dense. However, the method is very labor intensive.
Both of the reserve space problems mentioned above for the reserve cell approach are eliminated with the integrated function approach since there are no input/output cells to reserve unused areas. However, achievable density is still limited because the circuits of one input/output circuit must still be spaced apart from circuits of other input/output circuits in anticipation of possible circuit interference (layout interference). A diffusion region connected to the outside must be widely separated from another diffusion of arbitrary type, possibly with a guard ring or two interposed. This is necessary to avoid latch-up. Packaging within a circuit is customized, but differing functions that have been packed side by side may result in form factor conflicts that also result in a loss of total density.
One type of technique that has been developed for integrated circuit layouts is termed "bit stack layout". According to the bit stack layout philosophy, the location of circuits is dictated by the wiring of those circuits. Traditionally, integrated input/output circuits in bit stack configured semiconductor devices, are located on the peripheral of the chip. In small scale integrated circuit designs this was not a problem, since the edge of the chip was not far from any of the other circuits on the chip. However, in very large scale integration (VLSI), the edge is a distinct location different from the inside portions of the chip. However, the input/output functions have still been located at the edge because (1) the input/output circuits were close to the integrated circuit package connection pads, (2) busses that feed the input/output circuitry include the power busses which have traditionally been placed at the edge since they do not have to be fed through the internal circuitry, (3) in complimentary MOS integrated circuits, a parasitic effect termed "latch-up" exists and in order to protect the internal chips from latch-up the input/output circuits (which are more susceptible to latch-up due to the incoming voltage variances caused by the interconnection to the outside environment) are located such that they are spaced and isolated by guard rings from the internal circuits which has resulted in their placement at the edge, and (4) the input/output circuits are large and traditional packaging design dictates that the small circuits be placed together to reduce wire size and to place large circuits elsewhere.
An example of bit stack architecture is disclosed in U.S. Pat. No. 4,006,492 entitled, "High Density Semiconductor Chip Organization". This patent illustrates a semiconductor chip layout method that provides for plurality of logic cells that have been arranged in columns. Another example is U.S. Pat. No. 3,999,214 entitled, "Wireable Planar Integrated Circuit Chip Structure", which shows circuit functions arranged in cells and the cells arranged in an orthogonal array of cells that are substantially parallel in both orthogonal directions. Another example is U.S. Pat. No. 3,798,606 which teaches a substrate providing electrical interconnection paths for several monolithic circuit modules, where each of the circuit modules is associated with distinct bits for data processing by internal circuitry. A further example is U.S. Pat. No. 3,968,478 entitled, "Chip Topography for MOS Interface Circuit". This patent teaches a partial custom layout of peripheral input/output circuits while illustrating internal circuit design using bit stack methodology. Japanese patent application No. 58-137229 entitled, "Semiconductor Device" (Abstract), illustrates a circuit layout that teaches a wiring optimization technique that teaches separate placement of input/output circuits.
Lastly, European Patent Application No. 0 052 828 illustrates internal circuits laid out in a bit stack structure, but also shows that the input/output circuits are arranged as reserved cells along the peripheral locations of the chip.
The above bit stack structure examples unanimously teach the layout of input/output circuits as non-integrated circuit elements and, further, provide for their location on the peripheral areas of the integrated circuit. It is the object of the present invention to provide for a method and layout of integrated input/output circuits that enhances the density of the integrated input/output circuits in the total integrated circuit chip layout.